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Integrated Circuit Systems, Inc.
ICSSSTUB32872A
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28-Bit Registered Buffer for DDR2
Recommended Application: * DDR2 Memory Modules * Provides complete DDR DIMM solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A * Optimized for DDR2 400/533/667 JEDEC 4 Rank VLP DIMMS Product Features: * 28-bit 1:1 registered buffer with parity check functionality * Supports SSTL_18 JEDEC specification on data inputs and outputs * Supports LVCMOS switching levels on RESET input * 50% more dynamic driver strength than standard SSTU32864 * Low voltage operation VDD = 1.7V to 1.9V * Available in 96 BGA package
Pin Configuration
1 A B C D E F G H J K L M N P R T 2 3 4 5 6
96 Ball BGA (Top View)
Functionality Truth Table
In puts RESET H H H H H H H H H H H H L DCS0 L L L L L L H H H H H H X or floating DCS1 L L L H H H L L L H H H X or floating CK L or H L or H L or H L or H X or floating CK L or H L or H L or H L or H X or floating Dn, DODTn, DCK En L H X L H X L H X L H X X or floating Qn L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L Outputs QCS L L Q0 L L Q0 H H Q0 H H Q0 L QODT, QCKE L H Q0 L H Q0 L H Q0 L H Q0 L
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ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICSSSTUB32872A
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Ball Assignments 28 bit 1:1 Register
A DCKE0 D0 B DCKE1 D1 C D2 E
D3 DODT1 V REF GND V DD V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD V DD QCKE0 Q0 Q2 QODT0 Q3 Q5 NC QCS0 NC Q7 Q9 Q11 Q13 Q15 Q17 Q19 QCKE1 Q1 Q21 QODT1 Q4 Q6 NC QCS1 NC Q8 Q10 Q12 Q14 Q16 Q18 Q20
D DODT0 PTYERR GND
D4 D6 V DD GND
F D5 H CK J CK K L
D7 D9
G PAR_IN RESET V DD
DCS0 DCS1 D8 D10 D12 D14 D16 D18 D20 GND V DD GND V DD GND V DD GND V DD D21
M D11 N D13 P D15 R D17 T D19 1
2
3
4
5
6
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ICSSSTUB32872A
Advance Information
General Description
This 28-bit 1:1 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The ICSSSTUB32872A operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low. The device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the ICSSSTUB32872A must ensure that the outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when both DCS0 and DCS1 are high. If either DCS0 or DCS1 input is low, the Qn outputs will function normally. The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs low and the PTYERR output high. The ICSSSTU32872A includes a parity checking function. The ICSSSTUB32872A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW). Package options include 96-ball Thin Profile Fine Pitch BGA (TFBGA, MO-TBD).
Inputs RESET H H H H H H H H H H L DCS0 L L L L H H H H H X X or floating DCS1 H H H H L L L L H X X or floating CK L or H X or floating CK L or H X or floating of inputs = H (D0-D21) Even Odd Even Odd Even Odd Even Odd X X X or floating PARIN* L L H H L L H H X X X or floating
Output PTYERR** H L L H H L L H
PTYERR 0 PTYERR 0
H
*
PARIN arrives one clock cycle after the data to which it applies.
** This transition assumes PTYERR is high at the crossing of CK going high and CK going low. If PTYERR is low, it stays latched low for two clock cycles or until RESET is driven low.
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ICSSSTUB32872A
Advance Information
Ball Assignment
Signal Group Signal Name Type Description DRAM function pins not associated with Chip Select. DRAM inputs, re-driven only when Chip Select is LOW. DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at least one will be low when a valid address/command is present. The register can be programmed to re-drive all D-inputs when at least one Chip Slect input is LOW. Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock.
Ungated inputs DCKE0, DCKE1, SSTL_18 DODT0, DODT1 Chip Select gated inputs Chip Select inputs D0 ... D21 DCS0 , DCS1 SSTL_18 SSTL_18
Re-driven outputs
Q0...Q21, QCS0-1, QCKE0-1, QODT0-1 PARIN
SSTL_18
Parity input
SSTL_18
Input parity is received on pin PARIN and should maintain odd parity across the D0...D20 inputs, at the rising edge of the clock. When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard DDR-II register with parity (in JEDEC definition). Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (CK). Asynchronous reset input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR signal.
Parity error output
PTYERR
Open drain
Clock inputs
CK, CK
SSTL_18
Miscellaneous inputs
RESET
1.8 V LVCMOS
VREF
0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins (internally tied together) are used for increased reliability.
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ICSSSTUB32872A
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Block Diagram
(CS ACTIVE) VREF PARITY GENERATOR AND CHECKER
PARIN
D R
Q 22
PTYERR
D0
D R
Q
Q0
D21
D R
Q
Q21
DCS0
D R
Q
QCS0
DCS1
D R
Q
QCS1
DCKE0, DCKE1
2 D R Q
2
QCKE0, QCKE1
DODT0, DODT1
2 D R Q
2
QODT0, QODT1
RESET CK CK
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ICSSSTUB32872A
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Parity Functionality Block Diagram
21 Dn D Q
21
Qn
D
D
LATCHING AND RESET FUNCTION see Note (1)
PTYERR
PARIN
D
(1) This function holds the error for two cycles. See functional description and timing diagram.
CLOCK
002aaa417
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ICSSSTUB32872A
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Register Timing
RESET
DCSn
n CK
n+1
n+2
n+3
n+4
CK
tACT
tsu
th
Dn (1) tPDM, tPDMSS CK to Q Qn
tsu
th
PARIN tPHL CK to PTYERR tPHL, tPLH CK to PTYERR
PTYERR
H, L, or X
H or L
Figure 4 --RESET switches from L to H
(1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a minimum time of t ACT (max) to avoid false error.
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ICSSSTUB32872A
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Register Timing
RESET
DCSn
n CK
n+1
n+2
n+3
n+4
CK tsu th
Dn (1) tPDM, tPDMSS CK to Q Qn tsu
th
PARIN tPHL, tPLH CK to PTYERR PTYERR
002aaa984
Unknown input e vent
Output signal is dependent on the pr unkno event ior wn
H or L
Figure 5 -- RESET being held HIGH
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ICSSSTUB32872A
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Register Timing
RESET
tINACT
DCSn
CK (1)
CK (1)
Dn (1) tRPHL RESET to Q
Qn
PARIN (1) tRPLH RESET to PTYERR PTYERR
H, L, or X
H or L
Figure 6 -- RESET switches from H to L
(1) After Reset is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic levels (not floating) for a minimum time of t INACT (max)
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ICSSSTUB32872A
Advance Information
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage1, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clamp Current . . . . . . . . . . . . . . . . . . . . Output Clamp Current . . . . . . . . . . . . . . . . . . . Continuous Output Current . . . . . . . . . . . . . . . VDD or GND Current/Pin . . . . . . . . . . . . . . . . -65C to +150C -0.5V to 2.5V -0.5V to VDD +2.5V -0.5V to VDDQ + 0.5V 50 mA 50mA 50mA 100mA Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This value is limited to 2.5V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
Package Thermal Impedance3 . . . . . . . . . . . . . . . 36C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Recommended Operating Conditions
PARAMETER VDDQ V REF V TT VI V IH (DC) V IH (AC) V IL (DC) VIL (AC) VIH VIL VICR V ID I OH I OL TA
1
DESCRIPTION I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage Data Inputs DC Input Low Voltage AC Input Low Voltage Input High Voltage Level RESET Input Low Voltage Level Common mode Input Range CK, CK Differential Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature
MIN TYP 1.7 1.8 0.49 x VDD 0.5 x V DD VREF - 0.04 V REF 0 VREF + 0.125 VREF + 0.250
MAX 1.9 0.51 x VDD VREF + 0.04 VDDQ
UNITS
VREF - 0.125 VREF - 0.250 0.65 x VDDQ 0.675 0.600 0.35 x V DDQ 1.125 -8 8 70
V
mA C
0
Guaranteed by design, not 100% tested in production. Note: Rst and Cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless Rst is low.
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ICSSSTUB32872A
Advance Information
Electrical Characteristics - DC
TA = 0 - 70C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated) SYMBOL PARAMETERS VOH VOL II All Inputs Standby (Static) IDD Operating (Static) CONDITIONS IOH = -8mA IOL = 8mA VI = VDD or GND RESET = GND VI = VIH(AC) or VIL(AC), RESET = VDD RESET = VDD, Dynamic operating VI = VIH(AC) or VIL(AC), (clock only) CLK and CLK switching 50% duty cycle. IO = 0 RESET = VDD, VI = VIH(AC) or VIL (AC), Dynamic Operating CLK and CLK switching (per each data 50% duty cycle. One data input) input switching at half clock frequency, 50% duty cycle VI = VREF 350mV Data Inputs VICR = 1.25V, VI(PP) = 360mV CLK and CLK VI = VDDQ or GND RESET VDDQ 1.7V 1.7V 1.9V 1.9V 150 TBD MIN 1.2 TYP MAX 0.5 5 200 UNITS V A A mA
A/clock MHz
I DDD
1.8V TBD A/ clock MHz/data
Ci
2.5 2 4.5
5 3.8
pF pF
Notes: 1 - Guaranteed by design, not 100% tested in production.
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7) VDD = 1.8V 0.1V PARAMETER UNIT MIN MAX dV/dt_r 1 4 V/ns dV/dt_f 1 4 V/ns 1 dV/dt_ 1 V/ns 1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
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ICSSSTUB32872A
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Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted) V DD = 1.8V 0.1V PARAMETERS SYMBOL MIN MAX f clock Clock frequency 410 tW Pulse duration 1 t ACT Differential inputs active time 10 t INACT tS Setup time Hold time tH Hold time Notes: Differential inputs inactive time Data before CK, CK DCS0, DSC1 before CK, CK, CSR high DCS, DODT, DCKE and Dn after CK, CK PAR_IN after CK, CK 0.6 0.7 0.6 0.5 ns ns ns 15 UNITS MHz ns ns ns
1 - Guaranteed by design, not 100% tested in production. 2 - For data signal input slew rate of 1V/ns. 3 - For data signal input slew rate of 0.5V/ns and < 1V/ns. 4 - CK/CK signal input slew rate of 1V/ns.
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted) Symbol Parameter Measurement Conditions MIN fmax tPDM Max input clock frequency 410 1.25 1.2 0.9 1.9 3 3 2 3 3 MAX Units MHz ns ns ns ns ns ns
Propagation delay, single CK and CK to Qn bit switching Low to High propagation tLH delay CK and CK to PTYERR High to low propagation tHL delay Propagation delay CK and CK to Qn tPDMSS simultaneous switching High to low propagation tPHL RESET to Qn delay Low to High propagation tPLH RESET to PTYERR delay 1. Guaranteed by design, not 100% tested in production.
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ICSSSTUB32872A
Advance Information
VDD
DUT TL=50 CK Inputs Test Point RL = 100 Test Point VCMOS RST Inp ut t in act IDD (see Note 2) LOAD CIRCUIT VDD VDD/2 VDD/2 0V t act 90% 10% VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES tw Inpu t VICR VICR LVCMOS RST Input VIH VDD /2 t RPHL t su Inpu t VREF th VREF VIH VOH Output VTT V OL VIL VID Output VTT V TT CK VICR CK t PLH t PHL VOH VOL VICR CK CK TL=350ps, 50 Out CL = 30 pF (see Note 1) RL = 1000 Test Point RL = 1000
V ID
VOLTAGE WAVEFORMS - PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS - PULSE DURATION VID CK VICR CK
VIL VOLTAGE WAVEFORMS - SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS - PROPAGATION DELAY TIMES
Figure 6 -- Parameter Measurement Information (VDD = 1.8V 0.1V)
Notes: 1. CL incluces probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA. 3. All input pulses are supplied by generators having the following chareacteristics: PRR 10 MHz, Zo=50, input slew rate = 1 V/ns 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VREF = VDD/2 6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600 mV 9. tPLH and tPHL are the same as tPDM.
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ICSSSTUB32872A
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VDD DUT RL = 50 Out C L = 10 pF (see Note 1) Test Point
LOAD CIRCUIT - HIGH-TO-LOW SLEW-RATE MEASUREMENT Output 80% 20% dv _f dt _f VOL VOH
VOLTAGE WAVEFORMS - HIGH-TO-LOW SLEW-RATE MEASUREMENT
DUT
Out CL = 10 pF (see Note 1)
Test Point RL = 50
LOAD CIRCUIT - LOW-TO-HIGH SLEW-RATE MEASUREMENT dv _r dt _r 80% 20% Output VOL VOLTAGE WAVEFORMS - LOW-TO-HIGH SLEW-RATE MEASUREMENT VOH
Figure 7 -- Output Slew-Rate Measurement Information (VDD = 1.8V 0.1V)
Notes: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified).
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ICSSSTUB32872A
Advance Information
3 Test circuits and switching waveforms (cont'd) 3.3 Error output load circuit and voltage measurement information (VDD = 1.8 V 0.1 V) All input pulses are supplied by generators having the following characteristics: PRR Zo = 50 ; input slew rate = 1 V/ns 20%, unless otherwise specified. 10 MHz;
VDD DUT RL = 1K Out CL = 10 pF (see Note 1) Test Point
LOAD CIRCUIT - HIGH-TO-LOW SLEW-RATE MEASUREMENT (1) CL includes probe and jig capacitance.
Figure 28 -- Load circuit, error output measurements
LVCMOS RST Input t PLH Output Waveform 2
V CC V CC /2 0V V OH 0.15 V ___________ 0V
Figure 29 -- Voltage waveforms, open-drain output low-to-high transition time with respect to reset input
V I(PP) Timing Inputs tPHL Output Waveform 1 VICR V ICR
___________
V CC /2
V CC V OL
Figure 30 -- Voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs
V I(PP) Timing Inputs tPHL Output Waveform 2 V OH 0.15 V 0V VICR VICR
Figure 31 -- Voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs
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ICSSSTUB32872A
Advance Information
3 Test circuits and switching waveforms (cont'd) 3.4 Partial-parity-out load circuit and voltage measurement information (VDD = 1.8 V 0.1 V) All input pulses are supplied by generators having the following characteristics: PRR Zo = 50 ; input slew rate = 1 V/ns 20%, unless otherwise specified. 10 MHz;
DUT
Out
Test Point CL = 5 pF (see Note A) RL = 1 k
(1) CL includes probe and jig capacitance.
Figure 32 -- Partial-parity-out load circuit,
CK VICR CK tPLH tPHL VOH OUTPUT VTT VOL
002aaa375
VICR
Vi(p-p)
VTT = VDD/2 tPLH and tPHL are the same as tPD. VI(PP) = 600 mV
Figure 33 -- Partial-parity-out voltage waveforms; propagation delay times with respect to clock inputs
LVCMOS RST VIH INPUT VDD/2 VIL tPHL VOH OUTPUT VTT
002aaa376
VOL
VTT = VDD/2 tPLH and tPHL are the same as tPD. VIH = VREF + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = VREF - 250 mV (AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs.
Figure 34 -- Partial-parity-out voltage waveforms; propagation delay times with respect to reset input
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ICSSSTUB32872A
Advance Information
C Seating Plane A1 T b REF Numeric Designations for Horizontal Grid 4321 A B C D
D
Alpha Designations for Vertical Grid (Letters I, O, Q & S not used)
d TYP D1 - e - TYP TOP VIEW
E
h TYP 0.12 C
c REF E1
- e - TYP
ALL DIMENSIONS IN MILLIMETERS
----- BALL GRID ----Max. T e HORIZ VERT TOTAL d Min/Max Min/Max 13.50 Bsc 5.50 Bsc 1.20/1.40 0.80 Bsc 6 16 96 0.40/0.50 11.50 Bsc 5.00 Bsc 1.00/1.20 0.65 Bsc 6 16 96 0.35/0.45 Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. D E
h Min/Max 0.25/0.41 0.25/0.35
REF. DIMENSIONS b c 0.75 0.875 0.75 0.875
* Source Ref.: JEDEC Publication 95, 10-0055C
MO-205
Ordering Information
ICSSSTUB32872Az(LF)T
Example:
ICS XXXX y z (LF) T
Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type
H = LFBGA (reduced size: 5.5 x 13.50)
HM = TFBGA (reduced size: 5.0 x 11.50) Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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ICSSSTUB32872A
Advance Information
Revision History
Rev. A B C Issue Date Description 5/2/2006 Initial Release. Electrical table, Ci Data input max changed from 3.5 to 5.0, CLK max 12/12/2006 changed from 3 to 3.8 Timing table, ts Data before CK changed from 0.5 to 0.7, th DCS after CK 12/20/2006 changed from 0.5 to 0.6 Applications, removed "800"; Electrical table, Idd Operating max changed from 80 to 150, Ci RESET typ changed from 2.5 to 4.5; Timing table, th Hold 12/21/2006 Time, changed Q to Dn, Switching table, changed tpdm max from 1.7 to 1.9, thl min from 1 to 0.9, and tpdmss max from 1.9 to 2. 3/6/2007 3/13/2007 Timing table, ts Data before CK changed from 0.7 to 0.6; Switching table, fixed typos. Page 1, Recc. List, changed 3rd bullet to "Provides complete DDR DIMM solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A"; page 11, fixed typos. Page # 11 12
D
1, 11, 12
E F
12 1, 11
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